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  STT3471P -2a, -100v, r ds(on) 350 m ? p-channel enhancement mode mosfet elektronische bauelemente 08-apr-2011 rev. a page 1 of 2 http://www.secosgmbh.com/ any changes of specification will not be informed individually. rohs compliant product a suffix of ?-c? specifies halogen and lead-free description these miniature surface mount mosfets utilize a high cell density trench process to provide low r ds(on) and to ensure minimal power loss and heat dissipation. features ? low r ds(on) provides higher efficiency and extends battery life. ? low thermal impedance copper leadframe tsop-6 saves board space. ? fast switching speed. ? high performance trench technology. application dc-dc converters and power management in portable and battery-powered products such as computers, printers, pcmcia cards, cellular and cordless telephones. package information package mpq leader size tsop-6 3k 7? inch absolute maximum ratings (t a =25c unless otherwise specified) parameter symbol rating unit drain-source voltage v ds -100 v gate-source voltage v gs 20 v continuous drain current 1 t a = 25 c i d 2.0 a t a = 70 c 1.6 pulsed drain current 2 i dm -8 a continuous source current (diode conduction) 1 i s -2.1 a power dissipation 1 t a = 25 c p d 2.0 w t a = 70 c 1.3 operating junction and st orage temperature range tj, tstg -55~150 c thermal resistance rating maximum junction to ambient 1 t Q 5 sec r ? ja 62.5 c / w 110 notes: 1. surface mounted on 1? x 1? fr4 board. 2. pulse width limited by maximum junction temperature. ref. millimete r ref. millimete r min. max. min. max. a 2.70 3.10 g 0 0.10 b 2.60 3.00 h 0.60 re f . c 1.40 1.80 j 0.12 ref. d1.10 max. k 0 10 e 1.90 ref. l 0.95 ref. f 0.30 0.50 tsop-6 b l f h c j d g k a e 1 23 4 5 6 d g dd d s
STT3471P -2a, -100v, r ds(on) 350 m ? p-channel enhancement mode mosfet elektronische bauelemente 08-apr-2011 rev. a page 2 of 2 http://www.secosgmbh.com/ any changes of specification will not be informed individually. electrical characteristics (t a = 25c unless otherwise specified) parameter symbol min. typ. max. unit test conditions static gate-threshold voltage v gs(th) -1 - - v v ds = v gs , i d = -250 a gate-body leakage i gss - - 100 na v ds =0, v gs = 20v zero gate voltage drain current i dss - - -1 a v ds = -80v, v gs =0 - - -10 v ds = -80v, v gs =0, t j = 55 c on-state drain current 1 i d(on) -20 - - a v ds = -5v, v gs = -10v drain-source on-resistance 1 r ds(on) - - 350 m ? v gs = -10v, i d = -1.4a - - 450 v gs = -4.5v, i d = -1.2a forward transconductance 1 g fs - 2.8 - s v ds = -15v, i d = -1.4a diode forward voltage v sd - - -1 v i s = -1.4a, v gs =0 dynamic 2 total gate charge q g - 6 - nc v ds = -30v, v gs = -4.5v, i d = -1.4a gate-source charge q gs - 10 - gate-drain charge q gd - 3 - turn-on delay time t d(on) - 3 - ns v dd = -30v, v gen = -10v, r l =30 ? , i d = -1a, r g = 6 ? rise time t r - 3 - turn-off delay time t d(off) - 13 - fall time t f - 7 - notes: 1. pulse test pw Q 300 us duty cycle Q 2%. 2. guaranteed by design, not subject to production testing.


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